A GENERALIZED CODE FOR COMPUTING CYCLIC REDUNDANCY CHECK
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Abstract
This paper focuses on developing a generalized CRC code where the user can vary the size of the generator polynomial [1] such as 9 bits (CRC-8), 17 bits (CRC-16), 33 bits (CRC-32), 65 bits (CRC-64). The working of the code has been shown taking an example and the resulting simulations obtained are shown.
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References
1. Cyclic Redundancy Code (CRC) Polynomial Selection For Embedded Networks By Philip Koopman
and Tridib Chakravarty
2. CRC Cyclic Redundancy Check Analysing and Correcting Errors By Prof. Dr. W. Kowalk
3. VHDL basics By Raunak Ranjan
4. http://en.wikipedia.org/wiki/Cyclic_redundancy_check
and Tridib Chakravarty
2. CRC Cyclic Redundancy Check Analysing and Correcting Errors By Prof. Dr. W. Kowalk
3. VHDL basics By Raunak Ranjan
4. http://en.wikipedia.org/wiki/Cyclic_redundancy_check
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Published
Sep 26, 2015
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How to Cite
Ghosh, D., Mitra, A., Mukhopadhyay, A., Dawn, A., & Ghosh, D. (2015). A GENERALIZED CODE FOR COMPUTING CYCLIC REDUNDANCY CHECK. International Journal of Students’ Research in Technology & Management, 1(2), 192-202. Retrieved from http://giapjournals.com/index.php/ijsrtm/article/view/60
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IT & Computer Engineering
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