POWER REDUCTION IN MODERN VLSI CIRCUITS – A REVIEW
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Abstract
This paper focuses on the importance of reducing power consumption by VLSI circuits using different power reduction techniques. In this paper, various sources of power dissipation in modern VLSI circuits along with various power reduction techniques as adopted in industry today are discussed.
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References
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May, 2004 ,Wenxin Wang, 2004 Advisors: Professor Shawki Areibi, Mohab Anis
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CONTROL by Afshin Abdollahi, Farzan Fallah, and Massoud Pedram IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
VOL. 12, NO. 2, FEBRUARY 2004
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M.Chang, C.Chang,C.Chao, K.Goto,M.Leong, L.Lu,and C.Diaz Presented By Mozammel
Haque For the Low-Power High- Sped VLSI ELEC 5705Y W-2009
12. CMOS DIGITAL INTEGRATED CIRCUITS by Sung- Mo Kang and Yusuf Lablebici Tata
McGraw-Hill Education, 2003
13. SHORT CIRCUIT POWER REDUCTION BY USING HIGH THRESHOLD TRANSISTORS
by Arkadiy Morgenshtein Received: 15 October 2011; in revised form: 13 February 2012 /
Accepted: 21 February 2012 /Published: 1 March 2012 Journal of Low Power Electronics and
Applications ISSN 2079-9268 www.mdpi.com/journal/jlpea/
2. Massoud Pedram DESIGN TECHNOLOGIES FOR LOW POWER VLSI
3. www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch04.pdf by L Benini and G De Micheli
4. http://www.ee.ncu.edu.tw/~jfli/vlsi21/lecture/ch04.pdf by Jin-Fu Li; Advanced Reliable
Systems (ARES) Lab. D
5. epartment of Electrical Engineering, National National Central University Central
University, Jhongli, Taiwan
6. MICRO TRANSDUCTORS ’08 OW POWER VLSI DESIGN 2 by Dr.-Ing. Frank Sill;
Department of Electrical Engineering, Federal University of Minas Gerais, Av. Antônio
Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil franksill@ufmg.br,
ttp://www.cpdee.ufmg.br/~frank/
7. LOW POWER DESIGN: CLOCK GATING by M. Ohashi, Matsushita
8. LOW-POWER MULTI-THRESHOLD CMOS CIRCUITS OPTIMIZATION AND CAD
TOOL DESIGN
9. A Thesis Presented to The Faculty of Graduate Studies of The University of Guelph by
WENXIN WANG In partial fulfillment of requirements for the degree of Master of Science
May, 2004 ,Wenxin Wang, 2004 Advisors: Professor Shawki Areibi, Mohab Anis
10. LEAKAGE POWER REDUCTION IN CMOS VLSI CIRCUITS BY INPUT VECTOR
CONTROL by Afshin Abdollahi, Farzan Fallah, and Massoud Pedram IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
VOL. 12, NO. 2, FEBRUARY 2004
11. TRANSISTOR AND CIRCUIT DESIGN OPTIMIZATION FOR LOW-POWER CMOS By
M.Chang, C.Chang,C.Chao, K.Goto,M.Leong, L.Lu,and C.Diaz Presented By Mozammel
Haque For the Low-Power High- Sped VLSI ELEC 5705Y W-2009
12. CMOS DIGITAL INTEGRATED CIRCUITS by Sung- Mo Kang and Yusuf Lablebici Tata
McGraw-Hill Education, 2003
13. SHORT CIRCUIT POWER REDUCTION BY USING HIGH THRESHOLD TRANSISTORS
by Arkadiy Morgenshtein Received: 15 October 2011; in revised form: 13 February 2012 /
Accepted: 21 February 2012 /Published: 1 March 2012 Journal of Low Power Electronics and
Applications ISSN 2079-9268 www.mdpi.com/journal/jlpea/
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Published
Sep 26, 2015
Article Details
How to Cite
Ghosh, D., Guha, J., De, A., & Mukherjee, A. (2015). POWER REDUCTION IN MODERN VLSI CIRCUITS – A REVIEW. International Journal of Students’ Research in Technology & Management, 1(4), 361-369. Retrieved from http://giapjournals.com/index.php/ijsrtm/article/view/80
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Electronics Engineering
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